Resistive memory accelerator
US9847125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2016 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.