Biasing the substrate region of an MOS transistor
US9847349B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2017 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Mar 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.