Dead time adjusting circuit
US9847779B2 · kind B2 · utility
1Cited by
1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2016 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Feb 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a dead time adjusting circuit, a switch voltage appearing at a connection node between a first output switch and a second output switch, which are connected in series between two different potentials, is monitored to detect a first dead time, which is from a time at which the second output switch is turned off to a time at which the first output switch is turned on, and a second dead time, which is from a time at which the first output switch is turned off to a time at which the second output switch is turned on, each of the first and second dead times being feedback-controlled to be identical to a predetermined target value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.