Scalable architecture for IP block integration
US9847783B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2015 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Oct 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.