Analog dithering to reduce vertical fixed pattern noise in image sensors
US9848152B1 · kind B1 · utility
9Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 27, 2016 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Sep 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.