Round for reround mode in a decimal floating point instruction
US9851946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.