Techniques for scalable endpoint addressing for parallel applications
US9852107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2015 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jun 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.