Nonvolatile memory device, memory system, method of operating nonvolatile memory device, and method of operating memory system
US9852804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is performed on first memory cells connected to a first word line by using a first read voltage level. A read retry operation is, if the first read operation fails, performed on the first memory cells so that a read retry voltage level is set to a second read voltage level. A read offset table is determined based on a difference between the first read voltage level and the second read voltage level. The read offset table stores a plurality of read voltage offsets. A second read operation is performed on second memory cells connected to a second word line by using a third read voltage level determined using the read offset table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.