Method for producing an integrated circuit package and apparatus produced thereby
US9853007B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2015 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/17132
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.