System and method for temperature sensing of three-dimensional integrated circuit
US9857240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2015 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Mar 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01K1/16
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and a method for temperature sensing of three-dimensional integrated circuits are revealed. The three-dimensional integrated circuit is formed by stacking of a plurality of chip layers that execute specific functions. The chip layer includes a master layer and at least one slave layer. The master layer is disposed with a master temperature sensor while a first thermal conductive part is arranged at the slave layer where heat is detected. The first thermal conductive part and the master temperature sensor are connected by a thermal conductive structure. Thereby temperature of various points at different chip layers is conducted to the same chip layer by Through Silicon Vias to be measured and calibrated. The design complexity and the implementation cost of the temperature sensing system are significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.