Host interface controller and control method for storage device
US9857981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jun 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.