Solid state drive and flash translation layer table rebuilding method thereof
US9857983B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 5, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jun 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash translation layer table rebuilding method for a solid state drive is provided. The solid state drive includes a non-volatile memory and a buffering circuit. Firstly, a flash translation layer table is loaded from the non-volatile memory to the buffering circuit. In case that an abnormal shutdown event occurs, plural blocks of the non-volatile memory to be read are determined according to a specified block programming serial number of the flash translation layer table. Then, a read sequence of reading the plural blocks is determined according to a block programming serial number or an auxiliary serial number corresponding to the block. The contents of the blocks are read according to the read sequence. A mapping relationship between plural physical allocation addresses and plural logical block addresses of the flash translation layer table is updated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.