Wear leveling of a memory array
US9857986B2 · kind B2 · utility
7Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In at least one embodiment, a controller of a non-volatile memory array including a plurality of subdivisions stores write data within the non-volatile memory array utilizing a plurality of block stripes of differing numbers of blocks, where all of the blocks within each block stripe are drawn from different ones of the plurality of subdivisions. The controller builds new block stripes for storing write data from blocks selected based on estimated remaining endurances of blocks in each of the plurality of subdivisions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.