Patent · US Active

Computing architecture with concurrent programmable data co-processor

US9858220B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

Purdue Research Foundation · US

Inventors

Eugenio Culurciello · West Lafayette, US
Berin Eduard Martini · Lafayette, US
Vinayak Anand Gokhale · Austin, US
Jonghoon Jin · West Lafayette, US
Aysegul Dundar · Lafayette, US

Key dates

Filing date	Mar 17, 2015
Grant date	Jan 2, 2018
Priority date	—
Expiry date	Jan 21, 2036

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.