System transparent retimer
US9858234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2015 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Apr 5, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.