Nonvolatile RAM comprising a write circuit and a read circuit operating in parallel
US9858976B2 · kind B2 · utility
39Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.