Hardware-based performance equalization for storage devices
US9858990B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 18, 2014 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.