Memory test system and method of testing memory device
US9859023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jun 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.