Buffer with programmable input/output phase relationship
US9859901B1 · kind B1 · utility
12Cited by
60References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | May 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.