Interpolating feedback divider
US9859904B1 · kind B1 · utility
2Cited by
1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.