Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system
US9860088B1 · kind B1 · utility
6Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Dec 2, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.