Method and apparatus for compressing LUT
US9864699B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Apr 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.