Optimal sampling of data-bus signals using configurable individual time delays
US9864713B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Dec 3, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | May 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.