Operation instruction generating circuit and consumable chip
US9865314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation instruction generating circuit and a consumable chip. The operation instruction generating circuit includes: a power-on initialization module, connected to a signal wire and used for generating an initialization signal according to a signal transmitted by the signal wire; a middle signal generating module, connected to the power-on initialization module and the signal wire and used for combining, according to the initialization signal, the signal transmitted by the signal wire to generate a middle signal; and an instruction generating module, connected to the power-on initialization module and the middle signal generating module and used for generating an operation instruction according to the initialization signal and the middle signal or according to the initialization signal, the middle signal, and the signal transmitted by the signal wire. By the operation instruction generating circuit, the consumable chip is enabled to accurately respond to actions of a printing imaging device in time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.