Semiconductor memory devices having separate sensing circuits and related sensing methods
US9865342B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit of a semiconductor memory device is provided which includes a bit line having a first edge and a second edge, a sensing line, a current supply unit, and a sense amplifier. A plurality of memory cells is connected between the first edge and the second edge. The sensing line is connected to the second edge of the bit line, and the current supply unit supplies a sensing current via the first edge of the bit line. The sense amplifier senses data stored at a selected memory cell by comparing a sensing voltage of the sensing line with a reference voltage when the sensing current flows to the selected memory cell from the first edge of the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.