Semiconductor device layout having a power rail
US9865544B2 · kind B2 · utility
11Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Oct 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided as follows. An active region extends along a first direction. A gate line overlaps the active region and extending along a second direction intersecting the first direction. A power rail has a main pattern extending along the first direction and a sub-pattern branching off from the main pattern to extend along the second direction. A first source/drain contact, electrically connected to the power rail, overlaps the active region and the sub-pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.