Semiconductor device
US9865617B2 · kind B2 · utility
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10References
19Claims
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Key dates
| Filing date | Jan 10, 2017 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Jan 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.