Array substrate and a method for manufacturing the same
US9865622B2 · kind B2 · utility
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2Claims
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Key dates
| Filing date | Nov 29, 2013 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Nov 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate is disclosed. The array substrate comprises a base substrate (4) and signal lines on the base substrate (4). The signal lines comprises a plurality of conductive layers (11, 12) in different layers, and the plurality of conductive layers (11, 12) are provided with insulation layers (21) therebetween, and are connected in parallel through one or more vias (3). Embodiments of the present disclosure further disclose a method for manufacturing the array substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.