Method of simultaneously manufacturing partially shielded pixels

US9865636B2 · kind B2 · utility

Assignee

• STMicroelectronics (Grenoble 2) SAS · FR

Inventors

• Flavien Hirigoyen · Grenoble, FR
• Emilie Huss · Le Pont-de-Claix, FR

Key dates

• Filing date: Oct 11, 2016
• Grant date: Jan 9, 2018
• Expiry date: Oct 11, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/807

Abstract

A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a process wherein a first insulator is deposited on an active area. A first metal level is deposited and defined, with a first mask, to form a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield. A second insulator is deposited, and via openings therein are defined, with a second mask. An overlying second metal level is deposited and defined, with a third mask, to form two connection areas covering the via openings on each side of the first and second pixels. The second and third masks are identical for the first and second pixels.