Method for manufacturing laterally insulated-gate bipolar transistor
US9865702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Sep 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02271
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a so…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.