System and method for transistor voltage control
US9866018B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Oct 22, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Jul 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/08
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Systems and methods are drawn to controlling transistor gate voltages in load-switcher circuitry. A buffer may be applied to a load-switcher transistor to leverage the Miller effect. A slow gate charge circuit may be coupled to the gate of the transistor to control application of voltage to the gate and capacitances associated therewith. The buffer and slow gate charge circuit may be used in conjunction to control characteristics of the voltage applied to the gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.