Background calibration of interleave timing errors in time-interleaved analog to digital converters
US9866228B2 · kind B2 · utility
1Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Sep 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.