Interleaved successive approximation register analog to digital converter
US9866231B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Feb 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.