Apparatus and method for single antenna interference cancellation (SAIC) enhancement
US9866411B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Dec 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03426
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interference cancellation (IC) processor, a method, a method of manufacturing a semiconductor device, and a method of constructing an integrated circuit are provided. The IC processor includes a plurality of mono interference cancellation (MIC) filter estimation processors, each including a different equalizer offset k0 and an input for receiving a de-rotated signal, and providing an effective channel hres,i and an estimated filter pi; a plurality of filters, each including an input connected to the plurality of MIC filter estimation processors, and an output; a plurality of multipliers, each including a first input connected to the plurality of filters, a second input for receiving a weight, and an output; and a branch combiner including a plurality of inputs connected to the plurality of multipliers, a first output for providing a combined residual channel Hres, and a second output for providing a projected output y of the de-rotated signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.