Reducing power consumption in a multi-slice computer processor

US9870039B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Steven J. Battle · Austin, US
• Owen Chiang · Austin, US
• Sam Gat-Shang Chu · Round Rock, US
• Saiful Islam · Austin, US
• Dung Q. Nguyen · Austin, US
• David R. Terry · Austin, US
• Eula A. Tolentino · Austin, US

Key dates

• Filing date: Dec 15, 2015
• Grant date: Jan 16, 2018
• Expiry date: Mar 29, 2036

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.