Address collision avoidance in a memory device
US9870172B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2015 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Feb 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.