Control chip memory power sequence
US9870175B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2017 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.