Hardware acceleration wait time awareness in central processing units with multi-thread architectures
US9870256B2 · kind B2 · utility
2Cited by
3References
8Claims
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Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.