Memory device performing post package repair (PPR) operation
US9870293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Nov 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.