Method and apparatus for integrated circuit mask patterning
US9870443B2 · kind B2 · utility
25Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Apr 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.