Semiconductor device and manufacturing method thereof
US9870926B1 · kind B1 · utility
7Cited by
18References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1-xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1-yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1-zGez is formed on the second epitaxial layer. Z is smaller than y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.