RC-stacked MOSFET circuit for high voltage (HV) electrostatic discharge (ESD) protection
US9870939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2015 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/814
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.