Semiconductor device having mesh-patterned wirings
US9871027B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2015 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Aug 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a mesh-patterned power source wiring that supplies respective circuits with a power source voltage supplied to a plurality of locations at an outer periphery of the semiconductor device. The semiconductor device also includes a back-biasing wiring supplying, to a semiconductor substrate, a substrate voltage that controls a threshold voltage of a semiconductor element. The back-biasing wiring includes a upper layer mesh wiring that receives a supply of a substrate voltage, and a lower layer mesh wiring that is provided in a different wiring layer from the upper layer mesh wiring. The outer peripheries of the upper layer mesh wiring and the lower layer mesh wiring are connected to each other through plural vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.