Three-phase three-level inverter with reduced common mode leakage current
US9871436B1 · kind B1 · utility
7Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Nov 15, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/56
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A system and methods for reducing common mode leakage current for a three-phase three-level inverter using a single modulation waveform, implemented by a controller using a space vector diagram is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.