Differential phase adjustment of clock input signals
US9871504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Feb 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.