Patent · US Active

Shared memory interleavings for instruction atomicity violations

US9875108B2 · kind B2 · utility

2Cited by

5References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Gilles A. Pokam · Fremont, US
Rolf Kassa · Amberg, DE
Klaus Danne · Braunschweig, DE
Tim Kranich · Braunschweig, DE
Cristiano L. Pereira · Sunnyvale, US
Justin E. Gottschlich · Santa Clara, US
Shiliang Hu · Los Altos, US

Key dates

Filing date	Mar 16, 2013
Grant date	Jan 23, 2018
Priority date	—
Expiry date	Oct 13, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.