Timing violation resilient asynchronous template
US9875327B2 · kind B2 · utility
5Cited by
8References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 4, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Mar 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.