Contact resistance mitigation
US9875332B2 · kind B2 · utility
6Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 11, 2015 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Nov 27, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.