Gate driving circuit and driving method thereof, and display device
US9875712B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 7, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Apr 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2354/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit and a driving method thereof, and a display device are provided. The gate driving circuit comprises at least two stages of shift register units, and further comprises at least one compensation unit arranged between two adjacent shift register units; a scanning signal output terminal of a first shift register unit is connected to a first signal input terminal of the compensation unit; a first signal output terminal of the compensation unit is connected to a reset signal terminal of the first shift register unit; a scanning signal output terminal of a second shift register unit is connected to a second signal input terminal of the compensation unit; a second signal output terminal of the compensation unit is connected to a control signal input terminal of the second shift register unit; and the compensation unit is further connected to at least one compensation voltage terminal, a first voltage terminal and a second voltage terminal, and is configured to compensate for a gate scanning signal in blanking time. The phenomena of insufficient charging of the pixels caused by increase of the blanking time of the clock signal can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.