Refresh timer synchronization between memory controller and memory
US9875785B2 · kind B2 · utility
8Cited by
14References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Aug 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.